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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC145740
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Dual Tone Multiple Frequency Line Interface
The MC145740 is a silicon gate HCMOS LSI designed for general purpose Dual Tone Multiple Frequency (DTMF) communications, and contains a DTMF signal generator and a receiver for all 16 standard digits. The generator block has a differential line driver which drives a 600 load with 0 dBm level. The transmit signal level is adjusted in 1 dB steps by the programmable attenuator. The receiver block has an Auto Gain Control (AGC) amplifier to demodulate 50 dB (typ) dynamic range of DTMF signals to the hexadecimal codes. The device also includes a serial control interface that permits a CPU to exercise the following built-in features. * * * * * * * Single Power Supply: 3.6 to 5.5 V DTMF Generator and Receiver for All 16 Standard Digits 0 dBm Line Driver Into 600 Load AGC Amplifier Programmable Transmit Attenuator Serial Control Interface Power Down Mode, Less Than 1 A
20
1
F SUFFIX SOG PACKAGE CASE 751J
ORDERING INFORMATION
MC145740F SOG Package
PIN ASSIGNMENT
TxA1 TxA2 RxA AGCout Vref FC1 FC2 X1 X2 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DSI VDD VSS CLK EN DATA R/W TD DV VDD
BLOCK DIAGRAM
AGCout FC1 FC2
RxA
Rx GAIN CONTROL WITH AGC AMP
ANTI-ALIAS FILTER
HIGH-BAND BPF LOW-BAND BPF
TIMING CIRCUIT DTMF DETECTER
DV TD
DSI SMOOTHING FILTER AND Tx GAIN CONTROL EN CLK DATA R/W
TxA2 TxA1 -1
- +
DTMF GENERATOR
CONTROL REGISTER AND SERIAL INTERFACE
CLOCK GENERATOR
X1
X2
VDD
VSS
Vref
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 0 8/96
(c) Motorola, Inc. 1996 MOTOROLA
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Ratings Symbol VCC Vin I Value Unit V V DC Supply Voltage - 0.5 to + 7.0 Input Voltage, All Pins DC Current Per Pin Power Dissipation - 0.5 to VCC + 0.5 20 500 mA PD mW C Storage Temperature Range Tstg - 65 to + 150
MAXIMUM RATINGS (Voltages Referenced to VSS Unless Otherwise Noted)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Reliability of operation is enhanced if unused logic inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD).
RECOMMENDED OPERATING CONDITIONS
Parameter DC Supply Voltage Input Voltage, All Pins Input Rise or Fall Time Crystal Frequency Operating Temperature Range Symbol VCC Vin tr, tf fosc TA Min 3.6 0 0 -- - 20 Typ 5 -- -- 3.5795 25 Max 5.5 VCC 500 -- 70 Unit V V ns MHz C
DC ELECTRICAL CHARACTERISTICS (VCC = 5 V 10%, TA = - 20 to 70C)
Parameter Input Voltage EN, CLK, DATA, R/W Output Voltage DV, TD, DATA Input Current Supply Current H Level L Level H Level L Level R/W, DATA, EN, CLK Symbol VIH VIL VOH VOL Iin IDD IOH = 20 A IOL = - 20 A IOL = - 2 mA Vin = VDD or VSS DTMF Tx Mode DTMF Rx Mode Standby Current IDD Power Down 1 Power Down 2 Condition Min 3.15 -- VCC - 0.1 -- -- -- -- -- -- -- Typ -- -- VCC - 0.01 0.01 -- 1.0 5 8 -- -- Max -- 1.1 -- 0.1 0.4 10.0 -- -- 500 1 A A mA V Unit V
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MOTOROLA
AC ELECTRICAL CHARACTERISTICS
DTMF TRANSMIT CHARACTERISTICS (VCC = 5 V 10%, TA = - 20 to 70C)
Parameter Transmit Level Low Group High Group High Group Pre-Emphasis DTMF Distortion DTMF Frequency Variation Out-of-Band Energy (See Figure 1) Setup Time Symbol Vfl Vfh PE DIST fV VOE tosc Condition Attenuator = 0 dB fosc = 3.579545 MHz 3 579545 VTxA1 - VTxA2 RL = 1.2 k Min -- -- 0 -- -1 -- -- Typ 2.5 3.5 -- 5 -- -- 4 Max -- -- 3 -- 1 -- -- ms dB % % Unit dBm
TRANSMIT ATTENUATOR CHARACTERISTICS (VCC = 5 V 10%, TA = - 20 to 70C)
Parameter Attenuator Range Attenuator Accuracy Symbol ARNG AACC 1 dB - 5 dB 6 dB - 9 dB 10 dB - 15 dB Condition Min 0 - 0.5 -1 - 1.7 Typ -- -- -- -- Max 15 0.5 1 1 Unit dB dB
DTMF RECEIVER CHARACTERISTICS (VCC = 5 V 10%, TA = - 20 to 70C)
Parameter Input Impedance Detect Signal Level (Each Tone) Twist (High Group/Low Group) Frequency Detect Band Width Frequency Reject Band Width DTMF Detect Timing (See Figure 2) OFF to ON TVDON CD1 = 0, CD0 = 1 CD1 = 1, CD0 = 0 CD1 = 1, CD0 = 1 ON to OFF TVDOFF CD1 = 0, CD0 = 1 CD1 = 1, CD0 = 0 CD1 = 1, CD0 = 1 See Figure 3 Symbol RIDTMF Condition Min 50 - 48 - 10 1.5% 2 Hz -- -- -- -- -- -- -- Typ -- -- -- -- -- 20 30 40 20 30 20 Max -- 0 10 -- 3.5 -- -- -- -- -- -- ms Unit k dBm dB % fc
MOTOROLA
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SWITCHING CHARACTERISTICS (VCC = 5 V 10%, TA = - 20 to 70C, See Figure 4)
Parameter Pulse Width (H) Pulse Width (L) Clock Cycle Input Rise Time Input Fall Time Recovery Time Setup Time EN to SCK DATA to SCK R/W Low to DATA R/W High to DATA Hold Time SCK to DATA EN to R/W DATA to R/W R/W to DATA Read Data Delay Time EN to DATA SCK to DATA td th EN, SCK EN, SCK Symbol twh twl tc tr tf trec tsu Number 1 2 3 4 5 6, 18 7 9 12 8 10 14 15 13 17 Min 50 50 100 -- -- 50 50 100 50 50 50 50 50 -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 2 2 -- -- -- -- -- -- -- -- 50 50 ns ns Unit ns ns ns s s ns ns
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MOTOROLA
0 0
3.4 k 4 k
16 k
256 k
f (Hz)
TRANSMIT LEVEL (dBr)
- 25 - 15 dB/OCT.
- 55
Figure 1. Out-of-Band Energy
DTMF TONE CHANGED WITHOUT SILENT PERIOD
RxA
"A"
"B"
"C"
"D"
(NOTE 1) TD
ton
u 1 u 10 mS
ton DV
toff
(NOTE 2)
(NOTE 3) D0 - D3 "A" "B" "C" "D"
NOTES: 1. The high-to-low and low-to-high transition on the TD pin will appear immediately after the valid DTMF tones are detected. The TD will also output a short H pulse when the device detects the DTMF tones being changed without a silent period. 2. The high-to-low and low-to-high transition on the DV pin will appear after the programmed guard time determined by two bits of serial data (CD1, CD0). 3. The device recognizes the DTMF tones changed without a silent period, and the four bits of data can be read from the status register.
Figure 2. DTMF Detect Timing
NO DETECT
DETECT MINIMUM WIDTH
NO DETECT
- 3.5%
- 1.5% - 2 Hz LO
+ 1.5% + 2 Hz
Figure 3. DTMF Frequency Detect Band Width
MOTOROLA
IIIII IIIII IIIII
+ 3.5%
IIIIII IIIIII IIIIII
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CONTROL REGISTER 1 EN (NOTE 6) 6 1 7 9 DATA T3 8 T2 T1 2 3 2 1 T0 A3 A2 A1 4 A0 CD1 CD0 SQ M2 M1 M0 10 R/W 3 4 5 6 7 8 9 10 5 11 12 7 13 14 (NOTE 1)
CLK
(LSB CLOCK)
STATUS REGISTER 11 EN (NOTE 6) 12 CLK 17 13 DATA D0 D1 D2 18 (NOTE 5) 1 2 2 1 D3 (NOTE 2) 4 D0 14 16 R/W (NOTE 4) D1 D2 3 3 4 0 1 2 1 5 (NOTE 3) D0 D1 HIGH IMPEDANCE 15 5
NOTES: 1. The data in front of the EN signal will be latched. 2. The latched data will be repeated until there is an EN pulse. 3. The detected data will be updated with the next EN pulse. 4. After the R/W pin becomes inactive, the data will be lost. 5. D1 corresponds to CLK1. 6. The EN and CLK signals need to be set at the logic low level when the R/W signal changes. 7. The CLK signal must be held low when the EN signal is high.
Figure 4. Serial Interface Timing
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MOTOROLA
PIN DESCRIPTIONS
TxA1 Non-Inverting Analog Output (Pin 1) This pin is the line driver non-inverting output. A + 7 dBm (typ) differential output voltage can be obtained by connecting a 1.2 k load resistor between TxA1 and TxA2. Note that the DSI input, if used, must be controlled for the output level not to exceed the above signal level. TxA2 Inverting Analog Output (Pin 2) This pin is the driver inverting output. Refer to TxA1. RxA DTMF Receive Input (Pin 3) This pin is the DTMF signal input (AGC input). AGCout AGC Output (Pin 4) This pin is the AGC amplifier output. The signal received from the RxA pin appears at this pin through the AGC amplifier so that any signal receivers can be connected on this pin to decode the non-DTMF signals. The AGC amplifier gain is software programmable as shown in Table 3. Vref Reference Analog Ground (Pin 5) This pin provides the analog ground voltage, VCC/2, which is internally regulated from V CC . This pin should be decoupled to GND with 0.1 F and 100 F capacitors. FTLC1, FTLC2 Band-Pass Filter Test (Pins 6, 7) These pins are high impedance filter outputs. They may be used for testing the DTMF receive high and low band-pass filter characteristics, and are reserved for manufacturer's use only. In normal operation, each pin is decoupled to Vref with 0.1 F capacitors. X1 Crystal Oscillator Output (Pin 8) A 3.579545 MHz 0.1% crystal oscillator is tied to this pin with the other end connected to X2. X2 Crystal Oscillator Input (Pin 9) A 3.579545 MHz 0.1% crystal oscillator is tied to this pin with the other end connected to X1. X2 may be driven directly from an appropriate external clock source. In this case, X1 should be held open. GND Ground (Pins 10, 18) Ground pins are connected to the system ground. VCC Power Supply (Pins 11, 19) The digital supply pins are connected to the positive power supply (5 V). DV DTMF Data Valid (Pin 12) This pin goes low when valid DTMF tones are detected. The guard time of DTMF tone detection (ton) and release
(toff) is programmed by two bits of serial data (CD1, CD0) as shown in Table 2. This feature improves the immunity to the short noise and momentary dropouts. See Figure 2 for the detailed timing diagram. TD Tone Detect (Pin 13) This pin goes low immediately after valid DTMF tones are detected, regardless of the guard time set by two bits of serial data. This pin also outputs the short high pulse when the device detects the change of DTMF tones without a silent period. For a detailed description, see Figure 2. R/W Read/Write Data Switch (Pin 14) This pin is used for controlling the input/output direction of the DATA I/O pin. DATA Serial Data Input/Output (Pin 15) When the R/W pin is at logic low, the DATA pin works as the 14-bit control register input which determines the function mode, DTMF tones, transmit level (or receiver gain level), detect time, and transmit squelch. When the R/W pin is at logic high, the DATA pin works as the 4-bit status register output which provides the hexadecimal codes corresponding to the detected digit. EN Enable Input (Pin 16) When the R/W pin is held low, high level input to this pin transfers the 14 bits of control register data to the mode control logic, then the function mode is immediately changed. When this pin is at logic low, the control register and the mode control logic are isolated. Therefore, the 14 bits of data in the control register must not be changed while EN is at logic high level. When the R/W pin is held high, the rising edge of the EN pin loads the DTMF data from the DTMF decoder into the status register, and shifts out the first bit (LSB = D0) to the DATA pin. CLK SPI Clock Input (Pin 17) This pin is the SPI clock input for the 14-bit control register and the 4-bit status register. At the rising edge of CLK, the 14 bits of data are captured into the control register when R/W is at logic low, and the 4 bits of data are shifted out from the status register when R/W is at logic high. DSI Driver Summing Input (Pin 20) This pin is the inverting input of the line driver. An external signal source may be connected to this pin through a series resistor RDSI, transmitting the signal from the TxA1 and TxA2. The differential gain GDSI = (VTxA1 - VTxA2)/VDSI is determined by the following equation: GDSI = - 2 RF/RDSI, RF - 20 k Note that the programmable transmit attenuator does not affect this case. The DSI pin should be held open when not in use.
MOTOROLA
MC145740 7
SERIAL DATA INTERFACE
REGISTER MAP DESCRIPTION The timing diagram of the 14-bit control register input and the 4-bit status register output is shown in Figure 4. When the R/W pin is at logic low (write is selected), the control register is enabled. The 14 bits of data are captured into the control register at the rising edge of SCK. The 14 bits of data in the control register are transferred to the mode control logic at logic high to the EN pin, and then the function mode is immediately changed. When the R/W pin is at logic high (read is selected), the status register is enabled to read out the decoded DTMF data. At the rising edge of EN, the four bits of data in the DTMF decoder are loaded into the status register, and the first bit (D0) is presented on the DATA pin. The next three bits are shifted out by following rising edges of CLK (see Figure 4). FUNCTION MODE (M2 - M0) These three bits (M2 - M0) determine the function mode shown in Table 1. Table 1. Function Mode Truth Table
M2 0 0 0 0 1 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 Function Mode DTMF Receive DTMF Transmit Single Tone Transmit Power Down 1 Power Down 2 Analog Loopback
Single Tone Mode (M2 - M0 = 0, 1, 0) The transmitter generates one of the eight frequencies of DTMF tones. The receiver is disabled. Power Down Mode (Mode 1: M2 - M0 = 0, 1, 1; Mode 2: M2 - M0 = 1, 0, 0) In Power Down Mode 1, all internal circuits except for the oscillator are disabled, so that all output pins except for the X1 are in high-impedance state. The device current is decreased to 500 A (max). In Power Down Mode 2, all internal circuits are disabled, so all output pins are in high impedance state. The device current is decreased to 1 A (max). Analog Loopback Mode (M2 - M0 = 1, 0, 1) The transmitter output is internally connected to the receiver input. TRANSMIT SQUELCH (SQ) When the SQ bit is 1, the DTMF and single tone transmission are disabled (squelch is selected). However, the transmit squelch does not affect the external signal input from DSI. DTMF TONE DETECT/REJECT TIME (CD1, CD0) The CD1 and CD0 bits determine DTMF tones detect time (ton) and release time (toff) of the DV pin, as shown in Table 2. The timing diagram is shown in Figure 2. Table 2. DTMF Detect Time Truth Table
DTMF Receive Mode (M2 - M0 = 0, 0, 0) The DTMF receiver is enabled. The transmitter is disabled. DTMF Transmit Mode (M2 - M0 = 0, 0, 1) The DTMF tone generator is enabled. The receiver is disabled.
CD1 0 0 1 1
CD0 0 1 0 1
ton (ms)
toff (ms)
Reserved 20 30 40 20 30 20
CONTROL REGISTER (R/W = "L") FUNCTION MODE TRANSMIT SQUELCH DTMF DETECT TIME TRANSMIT ATTENUATOR/AGC GAIN TRANSMIT FREQUENCY STATUS REGISTER (R/W = "H") RECEIVED TONE FREQUENCY : 4 BITS D3 D2 D1 D0 : 3 BITS : 1 BIT : 2 BITS : 4 BITS : 4 BITS M2 SQ CD1 A3 T3 CD0 A2 T2 A1 T1 A0 T0 M1 M0
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MOTOROLA
TRANSMIT ATTENUATOR/AGC GAIN (A3 - A0) The A3 - A0 bits determine the analog transmit level of DTMF tones. The transmit attenuator range is controlled from 0 to 15 dB in 1 dB steps as shown in Table 3. However, this attenuator does not affect the external signal source from DSI. These four bits also determine the AGC amplifier gain in DTMF receive mode. In normal operation, "automatic" may be selected so that the receiver's gain is automatically adjusted, corresponding to the input signal level.
TRANSMIT TONE FREQUENCY (T3 - T0) The T3 - T0 bits determine DTMF tone frequencies transmitted from TxA1 and TxA2 in DTMF transmit and analog loopback mode, and determine the single tone frequency in single tone mode. Tone frequency assignments for the T3 - T0 bits are shown in Table 4. RECEIVED TONE FREQUENCY (D3 - D0) The D3 - D0 bits provide hexadecimal codes corresponding to detected DTMF tones. Tone frequency assignments for the D3 - D0 bits are shown in Table 4.
Table 3. Transmit Attenuator/AGC Gain Set Truth Table
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Tx Attenuation (dB) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Rx AGC Gain (dB) - 5.0 - 2.5 0.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 Clamp Automatic -- -- --
MOTOROLA
MC145740 9
Table 4. Tone Frequency Truth Table
Tone Frequency (Hz) DTMF Tx/Rx Mode Frequency T3/D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 T2/D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 T1/D1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 T0/D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 High Group 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Low Group 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 Keyboard Equivalent 1 2 3 4 5 6 7 8 9 0 * # A B C D Single T Si l Tone Mode 697 697 697 770 770 770 852 1336 1477 1336 1209 1477 1633 1633 1633 941
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MOTOROLA
APPLICATION CIRCUIT
10 TIP * RING 600 : 600 600 TxA1 TxA2 RxA AGCout* Vref 0.1 F 0.1 F 100 F 0.1 F 3.579545 MHz FC1 FC2 X1 X2 GND DSI* VCC GND CLK EN DATA R/W TD DV VCC I/O PORT MCU 0.1 F RDSI 100 F +5V
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
* Protection Network
Reference Analog Ground
System Ground
* The external devices (i.e., modem) may be connected on these pins, using the built-in line interface circuit.
MOTOROLA
MC145740 11
PACKAGE DIMENSIONS
F SUFFIX SOG (SMALL OUTLINE GULL-WING) PACKAGE CASE 751J-02
-A-
20 11
M
-B-
1 10
G S 10 PL 0.13 (0.005)
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.12 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G J K L M S MILLIMETERS MIN MAX 12.55 12.80 5.10 5.40 --- 2.00 0.35 0.45 1.27 BSC 0.18 0.23 0.55 0.85 0.05 0.20 0_ 7_ 7.40 8.20 INCHES MIN MAX 0.494 0.504 0.201 0.213 --- 0.079 0.014 0.018 0.050 BSC 0.007 0.009 0.022 0.033 0.002 0.008 0_ 7_ 0.291 0.323
B
M
C D 20 PL 0.13 (0.005)
M
L TB
S
0.10 (0.004) -T- A
S SEATING PLANE
K J
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MC145740 12
*MC145740/D*
MC145740/D MOTOROLA

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